How Priority Encoders Convert Active Bits to Binary

A priority encoder is a combinational digital circuit that monitors multiple input lines, identifies the highest-order asserted input, and translates its position into a corresponding binary output code. Unlike standard encoders, which produce erroneous outputs if multiple inputs are simultaneously active, a priority encoder relies on built-in precedence logic to ignore all lower-priority active lines. This article breaks down the internal logic gating, the truth table mechanics, and the Boolean expressions that allow priority encoders to resolve conflicting inputs and output an accurate binary representation.

The Principle of Priority Resolution

In standard digital logic, a regular \(2^n\)-to-\(n\) encoder expects exactly one input line to be high at any given time. In real-world systems, multiple request lines often become active concurrently. A priority encoder resolves this contention by assigning fixed precedence to each input line, typically ranking higher-indexed lines over lower-indexed lines (e.g., \(D_3 > D_2 > D_1 > D_0\)).

When multiple lines are driven high, internal logic gates inhibit the signals of the lower-order inputs. The encoder achieves this by evaluating inputs in descending order of significance. If the highest-order line is active (\(1\)), it forces the internal logic to ignore the state of all lines below it, treating them as “don’t care” conditions (\(X\)).

Truth Table and Logic Mapping

To understand how active lines map to binary numbers, consider a classic 4-to-2 active-high priority encoder with inputs \(D_0, D_1, D_2, D_3\) and binary outputs \(Y_1, Y_0\), where \(D_3\) holds the highest priority.

• Zero Active Inputs: When no lines are asserted, the binary outputs are undefined, but a designated Valid bit (\(V\)) drops to 0 to signal an idle state.
• Single or Multiple Active Inputs: If \(D_3\) is 1, the output is immediately mapped to binary 11 (\(3_{10}\)), regardless of whether \(D_2, D_1,\) or \(D_0\) are active. If \(D_3\) is 0 and \(D_2\) is 1, the output maps to binary 10 (\(2_{10}\)), ignoring \(D_1\) and \(D_0\).

Boolean Logic Implementation

The translation from individual bit lines into binary code is governed by minimized Boolean equations derived via Karnaugh mapping (K-maps).

For the 4-to-2 encoder, the output equations are:

• \(Y_1 = D_3 + D_2\) The most significant binary bit (\(Y_1\)) becomes 1 whenever either \(D_3\) or \(D_2\) is high, as both represent values \(\ge 2\).
• \(Y_0 = D_3 + (\overline{D_2} \cdot D_1)\) The least significant binary bit (\(Y_0\)) becomes 1 if \(D_3\) is active, or if \(D_1\) is active while \(D_2\) is inactive. This explicitly implements priority by using the inverted term \(\overline{D_2}\) to mask out \(D_1\) whenever \(D_2\) is asserted.
• \(V = D_3 + D_2 + D_1 + D_0\) The Valid output is an OR operation across all inputs, indicating whether any active request exists.

Hardware Scaling and Applications

To expand to larger bit-widths, such as an 8-to-3 or 16-to-4 priority encoder (e.g., standard ICs like the 74HC148), circuits use cascaded priority trees with Enable Input (\(EI\)) and Enable Output (\(EO\)) pins. These cascading signals propagate the detection of higher-order active bits down the chain to disable lower-stage sub-circuits.

This capability is essential in computer architecture for: * Interrupt Controllers (PICs): Identifying and routing the highest-priority hardware interrupt request to the CPU. * Flash Analog-to-Digital Converters (ADCs): Converting the parallel outputs of multiple voltage comparators into a single binary value. * Branch Prediction and Memory Allocation: Locating the first free block or most critical branch in arithmetic and logic units.