How MLC and TLC Flash Store Multiple Bits Per Cell

This article explains how Multi-Level Cell (MLC) and Triple-Level Cell (TLC) NAND flash memory architectures store multiple binary states within a single physical memory cell. By using precise voltage thresholds to trap varying amounts of electrons, these technologies divide a cell’s electrical capacity into distinct voltage windows. This mechanism allows a single cell to represent combinations of multiple binary bits, significantly increasing storage density compared to legacy single-bit storage methods.

The Foundation: Threshold Voltage and Charge Trapping

At the physical level, NAND flash memory consists of floating-gate transistors or charge-trap cells. When electrons are pushed into the floating gate or charge-trap layer via a process called Fowler-Nordheim tunneling, they create an electric field that changes the cell’s threshold voltage (\(V_{th}\)). The threshold voltage is the minimum control gate voltage required to make the transistor conduct electricity.

By varying the number of trapped electrons, the memory controller can precisely shift the cell’s threshold voltage into distinct, measurable ranges.

Mapping Binary States to Voltage Levels

Binary data consists of bits with values of 0 or 1. To store multiple bits per cell, the system uses \(2^n\) discrete voltage distributions, where \(n\) is the number of bits:

• Single-Level Cell (SLC): Stores 1 bit per cell (\(2^1 = 2\) states). It requires only two voltage distributions: erased (1) and programmed (0).
• Multi-Level Cell (MLC): Stores 2 bits per cell (\(2^2 = 4\) states). The available voltage range is divided into 4 distinct distributions, corresponding to the binary values 11, 10, 01, and 00.
• Triple-Level Cell (TLC): Stores 3 bits per cell (\(2^3 = 8\) states). The voltage range is divided into 8 narrower distributions, representing values from 111 down to 000 (111, 110, 101, 100, 011, 010, 001, 000).

The Write Process: Incremental Step Pulse Programming (ISPP)

To place a cell into a specific binary state, the flash controller must inject an exact quantity of electrons. This is achieved using Incremental Step Pulse Programming (ISPP).

During ISPP, the controller applies short, precise voltage pulses to push electrons into the storage layer, followed by a verify step to measure the resulting threshold voltage. If the target voltage level has not been reached, another slightly higher voltage pulse is applied. This loop repeats until the cell’s threshold voltage falls precisely within the designated target window for the intended binary combination.

The Read Process: Voltage Discrimination

To read the stored data, the memory controller applies intermediate reference voltages between the programmed distributions to the control gate:

1. MLC Read: The controller applies up to 3 reference voltages to determine which of the 4 voltage windows the cell falls into.
2. TLC Read: The controller applies up to 7 reference voltages to identify which of the 8 voltage windows the cell occupies.

Sensors detect whether electrical current flows through the transistor at each reference point. The controller translates the resulting conductive behavior back into the corresponding 2-bit (MLC) or 3-bit (TLC) binary pattern.

Trade-offs of Multi-State Storage

Dividing the finite operating voltage range into 4 (MLC) or 8 (TLC) states dramatically increases data density and lowers cost per gigabyte. However, it also narrows the safety margins between adjacent voltage levels.

As flash cells endure program and erase cycles, oxide degradation causes trapped electrons to leak, leading to voltage drift. Because the voltage gaps between states in TLC and MLC are much smaller than in SLC, even minor charge leakage can cause read errors, requiring sophisticated Error Correction Code (ECC) algorithms and Digital Signal Processing (DSP) to maintain data integrity.