How Bit-Slice Processors Build Custom Word Lengths

Bit-slice processors are modular computing building blocks that allow engineers to design central processing units (CPUs) with arbitrary, custom word lengths by cascading multiple smaller, fixed-width processing units. Rather than relying on a monolithic CPU with a fixed bit-width (such as 8, 16, or 32 bits), a bit-slice architecture uses standardized components—typically 2-bit or 4-bit wide—that are linked together horizontally. This modular approach provides the flexibility to create specialized computing hardware tailored for unique data precision requirements in telecommunications, digital signal processing, and high-performance computing.

The Modular Unit: The Bit-Slice Component

A single bit-slice integrated circuit contains a complete vertical section of a standard CPU datapath. It typically integrates: * An Arithmetic Logic Unit (ALU) capable of basic logic (AND, OR, XOR) and arithmetic operations (addition, subtraction). * A set of internal registers or a small register file. * Multiplexers for routing data between internal registers, external buses, and the ALU.

Because these internal components represent a slice of a larger binary datapath, they include input and output lines specifically designed for cascading, such as carry-in (\(C_{in}\)), carry-out (\(C_{out}\)), shift-left/right inputs, and status flag outputs.

Cascading Slices for Custom Word Lengths

To construct a custom-width processor, multiple bit-slices are placed in parallel. The total processor word length (\(N\)) is the sum of the widths (\(k\)) of all combined slices:

\[N = k \times \text{number of slices}\]

For example, using industry-standard 4-bit slices (such as the AMD Am2901): * Connecting two 4-bit slices produces an 8-bit processor. * Connecting four 4-bit slices produces a 16-bit processor. * Connecting six 4-bit slices produces a custom 24-bit processor. * Connecting nine 4-bit slices produces a non-standard 36-bit processor.

Interconnecting the Binary Datapath

When slices are chained together, binary operations are preserved across the entire custom word length through specific signal routings:

  1. Arithmetic Carry Propagation: The least significant slice receives the initial system carry-in. Its carry-out (\(C_{out}\)) is connected to the carry-in (\(C_{in}\)) of the adjacent slice. To avoid speed bottlenecks in wider word configurations, external Look-Ahead Carry (LAC) generators are often used to compute carries in parallel.
  2. Bit Shifts and Rotations: Shift-left and shift-right bidirectional pins are wired sequentially from slice to slice, allowing binary shift operations to propagate across the entire multi-chip datapath seamlessly.
  3. Condition and Status Flags: Status flags (such as zero, overflow, sign, and negative) are extracted from the most significant slice or computed collectively across all slices.

Microprogram Control

While the bit-slices handle the data execution path, they do not contain instruction decoding logic. Instead, a shared microprogram sequencer generates microinstructions that control all connected slices simultaneously. The identical control signals (microcode words) are broadcast to every slice, ensuring that all modular units execute the same operation on their respective binary segments during each clock cycle.

By separating the control logic from modular data-slice components, bit-slice processing allows system designers to scale binary precision directly to match application-specific algorithms without redesigning an entire CPU from scratch.