How ADCs Represent Signed Integers in Offset Binary

Analog-to-Digital Converters (ADCs) frequently handle bipolar analog signals—voltages that swing between negative and positive limits—by using the offset binary system, also known as excess-\(K\) or excess binary. This encoding method shifts the signed analog range into a strictly positive digital scale by adding a fixed bias value (the offset) equal to half of the total digital code range. Consequently, the minimum negative voltage maps directly to all binary zeros, the analog zero-crossing maps to the exact midpoint binary code, and the maximum positive voltage maps to all binary ones.

The Mechanics of Offset Binary Encoding

In a fixed-size \(n\)-bit binary representation, standard unipolar binary codes span from \(0\) to \(2^n - 1\). When dealing with bipolar analog signals (such as \(-V_{ref}\) to \(+V_{ref}\)), the ADC needs a way to assign unique codes to both negative and positive values.

The offset binary system solves this by setting the offset bias \(K\) to:

\[K = 2^{n-1}\]

For an \(n\)-bit ADC, a signed integer value \(X\) within the range \([-2^{n-1}, 2^{n-1} - 1]\) is represented as an unsigned binary integer \(D\):

\[D = X + 2^{n-1}\]

This calculation maps the signed range uniformly across the \(n\)-bit unsigned spectrum:

• Negative Full-Scale (\(-2^{n-1}\)): \(D = -2^{n-1} + 2^{n-1} = 0 \rightarrow \text{Binary: } 000\dots0\)
• Zero Input (\(0\)): \(D = 0 + 2^{n-1} = 2^{n-1} \rightarrow \text{Binary: } 100\dots0\)
• Positive Full-Scale (\(+2^{n-1} - 1\)): \(D = (2^{n-1} - 1) + 2^{n-1} = 2^n - 1 \rightarrow \text{Binary: } 111\dots1\)

4-Bit ADC Example

To illustrate, consider a 4-bit ADC (\(n = 4\)) with an offset \(K = 2^{4-1} = 8\):

Why ADCs Use Offset Binary Natively

Internal ADC architectures—such as Successive Approximation Register (SAR) and Flash ADCs—rely on comparator arrays and capacitive/resistive digital-to-analog converters (DACs) that measure voltages in a monotonic, linear sequence.

Because standard physical comparators simply detect whether a signal is higher or lower than a set reference point, the hardware naturally counts linearly from the lowest potential up to the highest potential. Outputting native offset binary eliminates the need for internal arithmetic logic units to calculate signs or negative representations at the hardware level, maximizing conversion speed and minimizing circuit complexity.

Converting Offset Binary to Two’s Complement

Most digital signal processors (DSPs) and microcontrollers process signed numbers using two’s complement arithmetic rather than offset binary.

Converting an \(n\)-bit offset binary number to standard two’s complement requires only inverting the Most Significant Bit (MSB). Because the sign bit in two’s complement is 0 for positive numbers and 1 for negative numbers—the exact inverse of the offset binary MSB—a single XOR gate on the MSB line converts native ADC offset binary output into two’s complement format instantly.