How a Half Adder Computes Binary Sum and Carry

A half adder is a fundamental digital logic circuit that performs the addition of two single-bit binary numbers. It produces two distinct outputs: the Sum (\(S\)) and the Carry (\(C\)). The circuit achieves this by combining two basic logic gates—an Exclusive-OR (XOR) gate to generate the Sum bit and an AND gate to generate the Carry bit. This article explains the underlying binary rules, logic gate operations, and truth table that allow a half adder to compute these values.

Binary Single-Bit Addition Rules

To understand the half adder, consider the four possible combinations when adding two single-bit binary numbers (\(A\) and \(B\)):

1. \(0 + 0 = 0\) (Sum: \(0\), Carry: \(0\))
2. \(0 + 1 = 1\) (Sum: \(1\), Carry: \(0\))
3. \(1 + 0 = 1\) (Sum: \(1\), Carry: \(0\))
4. \(1 + 1 = 10_2\) (Sum: \(0\), Carry: \(1\))

In the final case (\(1 + 1\)), the decimal result is \(2\), which is written as 10 in binary. This requires a two-digit output: the least significant bit (Sum) becomes \(0\), and the most significant bit (Carry) becomes \(1\).

Logic Gate Implementation

A half adder splits the operation into two distinct logic functions to handle the two outputs independently.

       A ──┬──────────────┐
           │              ├──[ XOR ]──── Sum (S)
       B ──┼───────┬──────┘
           │       │
           └──[ AND ]───────────── Carry (C)
                   │
                   └── (B input)

1. Computing the Sum with an XOR Gate

The Sum bit is high (\(1\)) only when the inputs are different (\(0+1\) or \(1+0\)). When both inputs are identical (\(0+0\) or \(1+1\)), the Sum bit is \(0\). This behavior perfectly matches the logic of an XOR (Exclusive-OR) gate:

\[\text{Sum} = A \oplus B\]

2. Computing the Carry with an AND Gate

The Carry bit is high (\(1\)) only when both inputs are \(1\) (\(1+1\)). For all other combinations, the Carry is \(0\). This behavior matches the logic of an AND gate:

\[\text{Carry} = A \cdot B\]

Half Adder Truth Table

The combined operation of the XOR and AND gates is summarized in the truth table below:

Limitations of a Half Adder

While a half adder efficiently adds two single-bit numbers, it has no input for a “Carry-in” (\(C_{in}\)) generated by a previous addition stage. Consequently, it cannot be directly chained to add multi-bit binary numbers where carrying from one column to the next is required. To overcome this limitation, two half adders and an OR gate are combined to create a Full Adder, which can process \(A\), \(B\), and an incoming Carry bit simultaneously.