Byte Boundaries and Word Alignment Explained

This article explores the fundamental relationship between byte boundaries and word alignment during CPU instruction execution within the binary number system. It examines how memory is structured at the binary level, why word alignment relies on specific binary address patterns, and how these concepts directly impact processor efficiency, instruction fetching, and hardware exception handling.

Understanding Byte Boundaries in Binary Memory

Computer memory is organized as a sequential array of 8-bit units called bytes. In the binary number system, every byte is assigned a unique binary address. A byte boundary represents the discrete start or end point of any single 8-bit memory cell. Because memory addresses are expressed as binary integers, consecutive byte boundaries increase by an increment of one in binary notation:

• Byte 0: ...0000_0000
• Byte 1: ...0000_0001
• Byte 2: ...0000_0010
• Byte 3: ...0000_0011

Every single byte can be uniquely located, but modern processors rarely fetch data or instructions one individual byte at a time.

Word Alignment in Binary Architectures

A machine “word” is the standard unit of data that a central processing unit (CPU) processes in a single operation. Common word sizes are 32 bits (4 bytes) or 64 bits (8 bytes).

Word alignment occurs when a multi-byte word is stored at a memory address that is an exact integer multiple of the word’s size in bytes. In binary arithmetic, this mathematical requirement translates directly to the state of the least significant bits (LSBs) of the memory address:

• 2-Byte Alignment (16-bit): Addresses must be multiples of 2. In binary, the last bit must be 0 (e.g., ...0010, ...0100).
• 4-Byte Alignment (32-bit): Addresses must be multiples of 4. In binary, the last two bits must be 00 (e.g., ...0100, ...1000).
• 8-Byte Alignment (64-bit): Addresses must be multiples of 8. In binary, the last three bits must be 000 (e.g., ...1000, ...0000).

When an address matches these bit patterns, it aligns perfectly with the physical wiring of the system’s memory bus.

The Relationship During Instruction Execution

The relationship between byte boundaries and word alignment governs how the CPU’s instruction fetch unit interacts with the memory bus.

1. Memory Bus Transfers and Bus Width

Hardware data buses are designed to transfer chunks of memory matching the native word size or cache line size along fixed byte boundaries. For a 32-bit system, the hardware reads 4 contiguous bytes starting only at addresses ending in 00 binary. If a 32-bit instruction is aligned, it resides entirely between two fixed 4-byte boundaries and is retrieved in a single memory cycle.

2. The Cost of Unaligned Execution

If a 32-bit instruction starts at an unaligned byte boundary (such as an address ending in 01, 10, or 11), the instruction spans across two separate physical words:

1. The CPU must execute two separate memory read cycles to fetch both words.
2. The internal logic must shift the retrieved binary data and mask out the unused bytes.
3. The remaining segments are merged into a single register before the instruction can be decoded.

This process introduces latency and reduces pipeline throughput.

3. Program Counter (PC) Binary Optimization

Because instructions on aligned architectures reside at fixed word boundaries, the Program Counter register does not need to increment by single byte steps. In a 32-bit fixed-length instruction architecture (such as ARM or RISC-V), instructions are always 4-byte aligned. Consequently, the CPU can hardwire the two lowest bits of the Program Counter to 00, simplifying branch calculations and instruction decode logic.

4. Architecture Enforcement

Different architectures handle unaligned byte boundaries differently during instruction execution:

• Strict Alignment (RISC architectures): The processor requires instruction fetches to be word-aligned. Attempting to execute an instruction from a non-aligned byte boundary triggers a hardware alignment fault (exception).
• Flexible Alignment (CISC architectures like x86): The processor supports unaligned instruction fetching across byte boundaries using internal micro-operations, trading execution speed and hardware complexity for code density.