CPU Cache Bandwidth Scaling With Core Frequency

This article explores how CPU L1, L2, and L3 cache bandwidth scales with core frequency during computer hardware benchmarking. It explains the direct, linear scaling of L1 and L2 caches, contrasts this with the decoupled clock domains often governing L3 cache, and breaks down how architectural differences impact synthetic benchmark results. Understanding these mechanics allows hardware enthusiasts and testers to accurately interpret performance metrics when overclocking or comparing processors.

The Fundamental Bandwidth Formula

To understand how cache scales during a benchmark, you must first understand how bandwidth is calculated. Cache bandwidth is the product of the data bus width (how much data can be moved in a single clock cycle) and the operating frequency (how many clock cycles occur per second).

Because the physical pathway (bus width) of a processor is fixed at the factory, the only variable that changes bandwidth in real-time is frequency. If a cache level can transfer 64 bytes per cycle, increasing the number of cycles per second directly increases the total gigabytes per second (GB/s) measured by benchmarking software.

L1 and L2 Cache: Linear Scaling

In modern CPU architectures, L1 and L2 caches are built directly into the CPU core itself. Because they are physically part of the core, they operate on the exact same clock domain as the core frequency.

During benchmarking, L1 and L2 cache bandwidth scales linearly with the CPU core clock:

  • 1:1 Ratio: If you increase the CPU core frequency by 10% through overclocking, the L1 and L2 cache bandwidth will also increase by approximately 10%.
  • Constant Cycle Latency: The number of clock cycles required to access L1 and L2 cache remains fixed regardless of frequency. Because the cycles happen faster at higher frequencies, overall latency measured in nanoseconds decreases, and data throughput increases proportionally.
  • Multi-Core Scaling: In multi-threaded cache benchmarks, total L1 and L2 bandwidth is the sum of the bandwidth of all active cores. Therefore, locking all cores to a high frequency yields massive linear gains in synthetic tests.

L3 Cache: Decoupled Domains and Interconnects

L3 cache behaves differently than L1 and L2 because it is a shared resource accessed by multiple cores. Depending on the CPU manufacturer and architecture, L3 cache may not run at the same frequency as the CPU cores.

Intel Architectures (Ring Bus / Uncore) On most modern Intel processors, the L3 cache operates on a separate clock domain known as the Uncore or Ring frequency.

  • If you increase the CPU core frequency but leave the Ring/Uncore frequency at its stock setting, L3 cache bandwidth will show very little improvement in benchmarks.
  • To see linear scaling in L3 bandwidth on these platforms, you must manually increase the Ring/Cache multiplier alongside the core multiplier.

AMD Architectures (CCX / Infinity Fabric) On modern AMD Ryzen processors, the L3 cache clock is typically tied to the core clock of the Core Complex (CCX).

  • Increasing the core frequency will linearly increase the L3 cache bandwidth, similar to L1 and L2.
  • However, if a benchmark forces a core to pull data from the L3 cache of a different core complex (on multi-chiplet CPUs), the bandwidth becomes bottlenecked by the Infinity Fabric interconnect frequency (FCLK) rather than the core frequency.

Interpreting Benchmark Results

When using benchmarking tools like AIDA64, Intel Memory Latency Checker (MLC), or SiSoftware Sandra, keep the following behaviors in mind to read your results accurately:

  • Boost Clock Fluctuations: Modern CPUs dynamically change frequencies based on thermal and power limits. A quick L1 test might run at maximum boost clocks, while a slightly longer L3 test might trigger mild thermal throttling, making L3 scaling appear worse than it actually is. Lock the CPU frequency in the BIOS for accurate scaling tests.
  • Single-Thread vs. Multi-Thread Saturation: A single core can easily saturate its own L1 and L2 cache bandwidth at any frequency. However, a single core often cannot fully saturate the entire shared L3 cache bus. Therefore, single-core L3 bandwidth benchmarks may not scale as aggressively with frequency as multi-core L3 benchmarks.
  • Instruction Sets: Benchmarks use AVX, AVX2, or AVX-512 instructions to maximize cache throughput. If a CPU is configured with an "AVX Offset" (which lowers core frequency when heavy instructions are detected), the cache bandwidth will drop proportionally to that offset during the benchmark.