dav1d SIMD on ARM and x86 for AVIF Decoding

This article examines whether the dav1d AV1 decoder executes Single Instruction, Multiple Data (SIMD) instructions on ARM and x86 architectures during AVIF image decoding. It details how the AVIF container format interacts with AV1 decoding pipelines, outlines the specific SIMD instruction sets utilized by dav1d across both hardware platforms, and highlights the decoding stages that benefit from hardware vectorization.

How dav1d Handles AVIF Image Decoding

The AV1 Image File Format (AVIF) uses the ISO Base Media File Format (ISOBMFF) container to store still images compressed using the AV1 video standard. Functionally, a still AVIF image is identical to an AV1 keyframe (intra-only frame).

AVIF parsing libraries, such as libavif, handle container demuxing and metadata extraction, but delegate the core pixel reconstruction directly to an AV1 decoder. When dav1d is configured as the underlying decode backend, it processes the image payload through its standard AV1 decoding pipeline. Because dav1d treats the payload as an intra frame, all of dav1d’s internal optimizations automatically apply to AVIF decoding.

SIMD Execution on x86 Processors

On x86 and x86-64 architectures, dav1d contains extensive hand-written assembly routines that automatically detect and execute supported SIMD instruction sets at runtime. During AVIF decoding on x86 hardware, dav1d executes:

• SSSE3 and SSE4.1: Baseline SIMD extensions used for older 64-bit processors to accelerate 8-bit and 10-bit/12-bit pixel operations.
• AVX2: The primary vectorization target for modern consumer x86 CPUs, processing 256-bit wide registers for significant speedups.
• AVX-512: Leveraged on compatible Intel Xeon and modern desktop processors (such as AMD Zen 4 and Intel with AVX-512 support) for 512-bit wide vector instructions, primarily optimizing high-throughput transform and filtering operations.

SIMD Execution on ARM Processors

On ARM architectures, dav1d provides comprehensive assembly implementations tailored for modern mobile, embedded, and desktop processors (such as Apple Silicon and ARM-based servers). When decoding AVIF images on ARM, dav1d executes:

• ARM NEON (ARMv7): 128-bit SIMD instructions on 32-bit ARM architectures.
• AArch64 NEON (ARMv8 / ARMv9): Highly optimized 64-bit ARM assembly that takes advantage of the expanded 32-register NEON file to process multiple pixels per instruction cycle.
• SVE / SVE2: Select modern ARM implementations utilize Scalable Vector Extensions for dynamic vector-length operations where available.

Accelerated Decoding Stages in AVIF

During AVIF image decompression, dav1d runs SIMD routines across several intensive pipeline stages:

1. Intra Prediction: Calculating directional and non-directional spatial predictions from neighboring reconstructed pixels.
2. Inverse Transforms (IDCT / ADST): Converting frequency-domain coefficients back into spatial-domain residual data.
3. Reconstruction: Adding residual values back to predicted pixel blocks.
4. Loop Filtering and CDEF: Applying the deblocking filter, Constrained Directional Enhancement Filter (CDEF), and Loop Restoration filters to eliminate blocking artifacts and preserve sharp edges.

Because these tasks are computationally identical in both AV1 video intra-frames and AVIF still images, dav1d fully executes native SIMD instructions on both ARM and x86 hardware throughout the entire AVIF decode process.