Why Apple Was Slow to Adopt AV1 Hardware Decoding

Despite joining the Alliance for Open Media (AOMedia) as a founding-level board member in 2018, Apple did not introduce hardware-accelerated AV1 decoding until late 2023 with the A17 Pro and M3 processors. While competitor platforms began introducing AV1 hardware support years earlier, Apple’s deliberate, gradual hardware roadmap was governed by strict architectural trade-offs, silicon transistor allocation priorities, thermal and battery efficiency standards, multi-year chip design cycles, and the availability of mature silicon intellectual property (IP).

Die Area Budgeting and Transistor Constraints

Every millimetre of silicon on an Apple A-series or M-series System on Chip (SoC) is tightly contested. Adding dedicated, fixed-function hardware decoders requires allocating physical die space and millions of transistors away from the CPU, GPU, or Neural Engine. In the late 2010s and early 2020s, the vast majority of consumer video was encoded in H.264 or HEVC (H.265). Dedicating silicon area to an AV1 decoder block offered minimal real-world performance return for the average user compared to expanding GPU compute units or cache sizes. Apple waited until the shift to advanced 3nm fabrication nodes provided the transistor density required to add AV1 decode blocks without sacrificing other essential compute logic.

Thermal Budgets and Power Efficiency Metrics

Software decoding of AV1 is notoriously compute-intensive, requiring significantly more processing power than HEVC. Apple’s product design philosophy strictly avoids software fallbacks that drain battery life or cause thermal throttling on mobile devices. Early iterations of third-party AV1 fixed-function decoder logic were not yet fully optimized for ultra-low-power mobile operation. Apple required a fully mature, power-efficient hardware implementation that met their internal efficiency-per-watt thresholds, ensuring that 4K and 8K AV1 playback would not adversely impact battery metrics on thin, fanless devices like the iPhone and MacBook Air.

Multi-Year Chip Development Cycles

Apple's silicon architecture roadmap operates on a three-to-four-year planning horizon. The AV1 specification was finalized by AOMedia in 2018, but stable, validated silicon-level IP cores suitable for high-volume consumer production were not widely available until 2020. Incorporating a new fixed-function hardware block into an existing microarchitecture requires extensive verification, silicon tape-out cycles, and deep integration with Apple's unified memory architecture. By the time the standard reached market maturity, the chips released between 2020 and 2022 (A14–A16 and M1–M2) had already locked their media engine architectures.

Ecosystem Maturity and Content Pipeline Needs

Apple prioritizes technologies that directly serve its closed ecosystem. The primary beneficiaries of AV1’s 20–30% compression efficiency advantage over HEVC were ultra-scale streaming platforms such as YouTube and Netflix, where bandwidth costs are massive. In contrast, Apple’s own services, including Apple TV+ and the native iOS/macOS camera pipelines, were already deeply optimized around HEVC. Because Apple controls both its hardware and operating system distribution, it faced less market urgency to support the new format until content providers significantly shifted their delivery streams to AV1.

Although AV1 was marketed as an open-source, royalty-free codec, it faced early legal challenges from external patent pools such as Sisvel, which claimed that AV1 infringed on various existing video compression patents. As a company with significant exposure to patent litigation, Apple historically approaches unproven licensing frameworks with caution. Delaying hardware implementation allowed the legal landscape surrounding AOMedia's royalty-free claims to stabilize before committing dedicated silicon logic to the standard.